Error Correction Codes (ECC) are used in a variety of applications, such as in various digital communication and data storage applications. Some ECC types, referred to as cyclic codes, can be represented by generator polynomials defined over a Galois field. Commonly-used examples of cyclic codes are Bose-Chaudhuri-Hocquenghem (BCH) codes and Reed-Solomon (RS) codes. Encoders of cyclic codes are often based on polynomial division. Several example encoder configurations are described by Lin and Costello in “Error Control Coding,” Prentice Hall, second edition, June, 2004, chapter 5, pages 146-149, and by Blahut in “Algebraic Codes for Data Transmission,” Cambridge University Press, 2004, chapter 8, pages 228-237, which are incorporated herein by reference.
In some applications of error correction coding, it is desirable that the encoder be configurable, i.e., be able to encode data with one of multiple different codes. Several types of configurable ECC encoders are described in the patent literature. For example, U.S. Pat. No. 7,478,310, whose disclosure is incorporated herein by reference, describes a programmable error correcting device. The device includes a controller, which receives information about a length of a codeword, an error correcting capacity, whether or not a shortened codeword mode is supported and a total byte number of burst data, and outputs a control signal. A preprocessor divides input information data by a length of information byte in a codeword and outputs the divided input information data in response to the control signal. A coder decides on a structure for encoding according to the control signal, and performs error correcting encoding on information data provided by the preprocessor according to the decided structure.
U.S. Pat. No. 6,385,751, whose disclosure is incorporated herein by reference, describes a programmable, reconfigurable Reed-Solomon encoder/decoder. The Galois Field order, the primitive polynomial and the number of symbols for each codeword are settable via writable registers. The decoder and encoder parameters are separately specified and the decoder and encoder can run simultaneously and independently.
U.S. Patent Application Publication 2009/0077449, whose disclosure is incorporated herein by reference, describes an encoder and a syndrome computer for cyclic codes, which process M codeword symbols per cycle where M is greater than or equal to one. The encoder and syndrome computer optionally further provide the configurability of a different M value for each cycle and/or the configurability of a different cyclic code for each codeword.
U.S. Pat. No. 6,353,909, whose disclosure is incorporated herein by reference, describes a configurable Reed-Solomon encoder. The encoder comprises a multiplexed multiplier-accumulator, a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator, a data/parity multiplexer coupled to the parallel latch bank, and an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer.
U.S. Pat. No. 6,631,488, whose disclosure is incorporated herein by reference, describes a configurable error detection and correction engine having a specialized instruction set tailored for error detection and correction tasks. The engine has a plurality of functional building blocks (e.g., a configurable convolutional encoding functional block, a convolutional configurable decoding functional block, and a configurable cyclic redundancy check (CRC) functional block) that can be programmed or configured.
U.S. Pat. No. 8,180,820, whose disclosure is incorporated herein by reference, describes generating a remainder from a division of a first polynomial by a second polynomial having a variable width. One or more embodiments include a first sub-circuit, a first adder, a second sub-circuit, and a second adder. The first sub-circuit is adapted to generate a first partial remainder, which has a fixed width greater than or equal to the width of the second polynomial, from the first polynomial excepting a least significant portion. The first adder is adapted to generate a sum of the least significant portion of the first polynomial and a most significant portion of the first partial remainder. The second sub-circuit is adapted to generate a second partial remainder from the sum. The second adder is adapted to generate the remainder from the second partial remainder and the first partial remainder excepting the most significant portion.